The present invention relates, in general, to a method for fabricating an MOS transistor and, more particularly, to a method for fabricating a MOS transistor, capable of forming a thin silicide film with once thermal annealing and forming a source/drain region of shallow junction by use of a common ion-implanting apparatus.
As the integration technology for semiconductor has been developed in the last few years, MOS transistors of not more than several microns can be integrated. As a result of high integration, the size of MOS transistor becomes more small and the junction depth of source/drain region in the MOS transistor comes to be more shallow.
However, since the area resistance of a junction is inversely proportional to the depth of the junction, as the depth of the source/drain region becomes shallower, the area resistance of the junction is larger, increasing the parasitic resistance of a device.
In an effort to reduce the parasitic resistance and to improve the characteristics of the device in fabricating a very highly integrated circuit, a silicide film has been proposed to be formed on the source/drain region.
The area resistance of junction is proportional to a specific resistance and is inversely proportional to the depth of junction. While the specific resistance of silicon is about 200 .mu..OMEGA..multidot.cm, that of the silicide film is around 50 .mu..OMEGA..multidot.cm even though a little difference is caused by its composition materials. Accordingly, taking advantage of the small specific resistance of the silicide, the area resistance of the shallow junction, a parasitic resistance, can be reduced.
As such a silicide film, a titanium silicide film is widely known to those skilled in the art.
Since the formation of titanium silicide film on a source/drain region results from the reaction of titanium with a silicon substrate constituting the junction as shown in the following formula, the formation of silicide film causes the source/drain region of silicon to consume in the amount corresponding to the thickness of the silicide film formed: EQU Ti+2Si.fwdarw.TiSi.sub.2
Accordingly, because the thickness of the silicide film formed, that is, the consumed portion of the source/drain region is considered as a part of the depth of the junction, there have been demanded a technology for the formation of thin, stable silicide film. In addition, the method is required to give electrical uniformity to the interface between the silicon and the silicide film formed in the source/drain region of shallow junction.
Silicide are largely grouped into a polycide, which is formed by the reaction of polysilicon with a refractory metal and into a self-aligned silicide (hereinafter "SALICIDE"), which results from the reaction of silicon with refractory metals.
Description for conventional fabrication processes for MOS transistor is to be given with reference to some figures for better understanding of the background of the present invention.
Referring initially to FIGS. 1A through 1E, there are illustrated conventional processes for fabricating a MOS transistor having a source/drain region of shallow junction on which a silicide film formed.
First, as shown in FIG. 1A, a conventional double diffusion process is applied to a substrate 11, so as to form a low density source/drain region 15 and a high density source/drain region 17. For this, so-called LOCOS process is carried out to form a field oxide film 12 which sections the substrate 11 into an active channel region and a device separation region and then, a gate insulating film 13 and a gate of polysilicon film 14 are formed on a predetermined portion of the channel region, in due order. The low density source/drain region 15 is formed by using the gate 14 as a mask in implanting impurities having an opposite, conductive type from the substrate 11. On the other hand, the high density source/drain region 17 is formed adjacent to the low density source/drain region 15 by using the gate 14 and a pair of spacers 16 formed at both side walls of the gate 14 as a mask in implanting an opposite, conductive type from the substrate 11.
FIGS. 1B and 1C illustrate the formation of a titanium silicide (TiSi) film. As illustrated in these figures, a titanium film 18, which is a kind of a refractory metal, is thinly deposited on the entire surface of the resulting structure of FIG. 1A and then, is subjected to a primary thermal annealing process at about 700.degree. C. During this primary thermal annealing, silicon atoms moves to the thin titanium film 18. That is, the reaction of the silicon atoms with the titanium occurs at the interface between the silicon substrate 11 and the thin titanium film 18 and the interface between the gate 14 of polysilicon and the thin titanium film 18, so as to form titanium silicide films 19 and 20 having a C.sub.49 phase.
Next, as shown in FIG. 1D, all non-reacted, remaining titanium film 18 is removed with a NH.sub.4 OH/H.sub.2 O.sub.2 solution. As mentioned above, the titanium silicide film 19 formed on the source/drain region 17 belongs to the SALICIDE, whereas the titanium silicide film 20 formed on the gate 14 has the property of polycide.
Finally, a secondary thermal annealing is applied at a temperature of not less than 800.degree. C., so as to form titanium silicide films 19' and 20' having a C.sub.54 phase, as shown in FIG. 1E. As a result, a MOS transistor is fabricated, wherein the thin titanium silicide film 19' is formed on the source/drain region 17 of shallow junction.
The reason that the above thermal annealing processes are separately carried out is as follows: if the thin titanium film formed is subjected to a metal thermal annealing process at a high temperature, the silicon atoms moves into the thin titanium film 18 and crosses over the spacers 16, so that not only is formed the titanium silicide film 19' of C.sub.54 phase on the source/drain region and the gate 14 but also unnecessary metal bridges 21 are formed across on the spacers 16. Since the metal bridges 21 are conductive, there is caused a short.
Therefore, the primary thermal annealing is carried out at a low temperature to form the titanium silicide film 19 of C.sub.49 only on the source/drain region 17 and then, non-reacted titanium film is removed so completely as not to form the metal bridges when the secondary thermal annealing process is performed at a high temperature to form the titanium silicide film 19' of C.sub.54 phase.
In the titanium silicide film, there are present two polymorphies. One is a titanium silicide of C.sub.49 (orthorhombic) structure, wherein lattice constant is a=3.62 .ANG., b=13.76 .ANG. and c=3.605 .ANG.. On the other hand, the other has a C.sub.54 (orthorhombic) structure, wherein lattice constant is a=8.236 .ANG., b=4.773 .ANG. and c=8.523 .ANG..
In the fabrication of semiconductor device, TiSi of C.sub.54 structure is employed owing to its stability and lower specific resistance.
To form the titanium silicide film on the source/drain region, as mentioned above, the source/drain region must be consumed a little because the thickness of the silicide film formed, that is, consumed portion of the region is included in the junction depth of the source/drain region.
Since the contact resistance is generally increased as the thickness of the silicide film is increased, it is preferred to form the silicide film in the thickness of not more than 300 .ANG..
For the sake of forming the thin silicide film, the titanium film is to be thinly deposited in a previous process. However, since the thin titanium film and the thin silicide film are inferior in thermal stability, agglomeration occurs in the sequential, secondary thermal annealing process, lowering the device characteristic.
In addition, owing to the thermal instability caused by the thin thickness of the titanium silicide film formed by the conventional processes, there are extensively generated bends at the interface between the titanium silicide film 19' and the source/drain region 17 of silicon.
Among methods for forming a thin silicide film on a source/drain region of shallow junction, a method using silicide as diffusion source, that is, SADS method has known to be most useful.
SADS method has been reported in J. electrochem. Sec., 139, 196, 1992. This SADS method comprises of forming previously a silicide film on a silicon substrate, implanting dopant ions in the silicide film and applying a thermal annealing process to the silicide film to diffuse the dopants in the silicide into the silicon substrate, thereby forming a source/drain of shallow junction. In process order, this method is different from the method illustrated in FIG. 1 in which a source/drain region is formed in advance of the formation of a silicide film.
With reference to FIGS. 3A through 3G, there are shown conventional fabrication processes for MOS transistor, using SADS process.
As shown in FIG. 3A, so-called LOCOS process is carried out to form a field oxide film 32 which sections a substrate 31 into an active channel region and a device separation region and then, a gate insulating film 33 and a gate of polysilicon film 34 are formed on a predetermined portion of the channel region, in due order. Subsequently, a pair of spacers 35 consisting of an insulating film are formed at both side walls of the gate 34.
FIGS. 3B through 3E illustrate the formation of a silicide film. This is similar to the silicide formation shown in FIGS. 1B through 1E. That is, on the resulting structure of FIG. 3A, there is deposited a thin titanium film 36 and then, a primary thermal annealing is carried out at 700.degree. C., forming a titanium silicide film 37 having the C.sub.49 phase at the interface between the titanium film 36 and the silicon substrate 31 as well as another titanium silicide film 38 at the interface between the gate 34 and the titanium film 36.
After non-reacted titanium film is completely removed with a NH.sub.4 OH/H.sub.2 O.sub.2 solution, a secondary thermal annealing process is carried out at high temperatures of not less than 800.degree. C., so as to transform the titanium silicide films 37 and 38 having C.sub.49 phase into titanium silicide films 37' and 38' having C.sub.54 phase.
Thereafter, as shown in FIG. 3F, using a low acceleration energy of about 10 KeV, dopant ions having an opposite, conductive type from the substrate are implanted in the titanium silicide films 37' and 38'. For example, in a p type substrate (NMOS), As.sup.+ ions are implanted. On the other hand, BF.sup.+ ions are implanted in an n type substrate (PMOS).
Finally, as shown in FIG. 3G, a thermal annealing process is carried out at about 1,000.degree. C., so as to diffuse the dopants implanted in the titanium silicide film 37' into the substrate 31.
As a result, a source/drain region 39 of shallow junction is formed along with the silicide film, finishing the fabrication of a MOS transistor.
This SADS method requires that, just after the ion-implantation, the dopants are to be distributed only in the titanium silicide film. The common ion-implanting process can be carried out only with the acceleration energy of not less than 30 KeV. If too large the ion-implanting energy is used, the dopants comes to be distributed even into the silicon substrate. This results in increase of leak current caused by a knock-on effect on ion-implantation.
To prevent the leak current, an ion-implanting apparatus using a low acceleration energy of around 10 KeV is required to be employed. However, the use of the low acceleration energy is disadvantageous in views of throughput and safety. For example, in order to distribute the dopants only in the titanium silicide film by use of the low acceleration energy of around 10 KeV, the substrate must be subjected into pre-amorphization by initially implanting dopants such as Ge.sup.+ in the substrate.
In addition, since thermal annealing is carries out twice to form the titanium silicide film in spite of the use of SADS method, there occur problems caused in the conventional method shown in FIG. 1.